Transistor structures and methods for making the same

ABSTRACT

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO 2 , or In 2 O 3 . A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, SnO 2  or In 2 O 3 , the substantially insulating ZnO, SnO 2 , or In 2 O 3  being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

PRIORITY CLAIM

This is a divisional of U.S. patent application Ser. No. 10/350,819,filed Jan. 24, 2003, which is a continuation-in-part of U.S. patentapplication Ser. No. 10/307,162, filed Nov. 27, 2002, which claimsbenefit of U.S. Provisional Application 60/382,696, filed May 21, 2002,all of which are incorporated herein be reference in their entireties.

FIELD

The present disclosure relates to transistor structures such as, forexample, transparent transistors.

BACKGROUND

The microelectronics industry and research community is undertakingefforts to fabricate electronic devices (e.g., diodes and transistors)that are transparent to the portion of the electromagnetic spectrum thatis visible to the human eye. Circuits made of such devices would offerunique opportunities for innovation or improvement of consumer-,automotive-, and military-electronics systems.

For example, active-matrix liquid crystal displays (AMLCD) are employedextensively in laptop computers and other information display products.The operation of an AMLCD display requires that each picture or displayelement (pixel) have a corresponding thin-film transistor (TFT)associated with it for selecting or addressing the pixel to be on oroff. Currently, AMLCD displays employ transistor materials that may bedeposited onto glass substrates but are not transparent (usuallyamorphous, polycrystalline, or continuous-grain silicon are thematerials used to fabricate TFTs on glass). Thus, the portion of thedisplay glass occupied by the addressing electronics is not availablefor transmission of light through the display. Therefore, theavailability of transparent transistors for AMLCD addressing wouldimprove display performance by allowing more light to be transmittedthrough the display.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain embodiments will be described in more detail with reference tothe following drawings:

FIG. 1 is a sectional view of a first embodiment of a presentlydisclosed transistor structure;

FIG. 2 is a sectional view of a second embodiment of a presentlydisclosed transistor structure;

FIG. 3 is a sectional view of a third embodiment of a presentlydisclosed transistor structure;

FIG. 4 is a graph showing drain-source current (I_(DS)) versusdrain-source voltage (V_(DS)), as a function of gate-source voltage(V_(GS)), for the transistor structure depicted in FIG. 1 (thegate-source voltage varies from +40V (top curve) to +2 V in 2 V steps);

FIG. 5 is a graph showing the I_(DS) vs. V_(GS) characteristics for thetransistor structure depicted in FIG. 1 at three different drain-sourcevoltages;

FIG. 6 is a graph showing inverter transfer characteristics for thetransistor structure depicted in FIG. 1 using a transparent thin-filmresistor load (R=70 MΩ) and a power supply voltage, V_(DD)=40 V;

FIG. 7 is a graph showing the optical transmission characteristicsthrough the source or drain portion of the transistor structure depictedin FIG. 1;

FIG. 8 is a sectional view of a fourth embodiment of a presentlydisclosed transistor structure;

FIG. 9 is a sectional view of a fifth embodiment of a presentlydisclosed transistor structure;

FIG. 10 is a sectional view of a sixth embodiment of a presentlydisclosed transistor structure;

FIG. 11 is a schematic representation of an example of a cell circuitfor an AMLCD that includes the presently disclosed transistor structure;

FIG. 12 is a schematic representation of an example of a dynamicrandom-access memory (DRAM) cell circuit that includes the presentlydisclosed transistor structure;

FIG. 13 is a schematic representation of an example of a logic inverterthat includes the presently disclosed transistor structure; and

FIG. 14 is a schematic representation of an example of an invertingamplifier circuit that includes the presently disclosed transistorstructure.

DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

For ease of understanding, the following terms used herein are describedbelow in more detail:

“Enhancement-mode transistor” means a transistor in which there isnegligible off-current flow, relative to on-current flow, between asource and a drain at zero gate voltage. In other words, the transistordevice is “normally off.” In contrast, a depletion-mode transistor is“normally on” meaning that more than a substantially negligible currentflows between a source and a drain at zero gate voltage.

“Gate” generally refers to the insulated gate terminal of a threeterminal FET when used in the context of a transistor circuitconfiguration.

“Substantially insulating” can include insulating materials (e.g.,materials having a resistivity of greater than about 10¹⁰ Ω-cm) andsemi-insulating materials (e.g., materials having a resistivity of about10³ Ω-cm to about 10¹⁰ Ω-cm).

“Substantially transparent” generally denotes a material or constructthat does not absorb a substantial amount of light in the visibleportion (and/or infrared portion in certain variants) of theelectromagnetic spectrum.

“Vertical” means substantially perpendicular to the surface of asubstrate.

The preceding term descriptions are provided solely to aid the reader,and should not be construed to have a scope less than that understood bya person of ordinary skill in the art or as limiting the scope of theappended claims.

Disclosed herein are enhancement mode, field effect transistors whereinat least a portion of the transistor structure may be substantiallytransparent. Devices that include the transistors and methods for makingthe transistors are also disclosed.

One variant of the transistor includes a channel layer comprising asubstantially insulating, substantially transparent, material selectedfrom ZnO, SnO₂, or In₂O₃. A gate insulator layer comprising asubstantially transparent material is located adjacent to the channellayer so as to define a channel layer/gate insulator layer interface.The transistor also includes a source that can inject electrons into thechannel layer for accumulation at the channel layer/gate insulator layerinterface and a drain that can extract electrons from the channel layer.

A second variant of the transistor includes a channel layer comprising asubstantially transparent material selected from substantiallyinsulating ZnO, substantially insulating SnO₂, or substantiallyinsulating In₂O₃, the substantially insulating ZnO, substantiallyinsulating SnO₂, or substantially insulating In₂O₃ being produced byannealing. A gate insulator layer is located adjacent to the channellayer and comprises a substantially transparent material. The transistoralso includes a source, a drain, and a gate electrode.

A method for making the transistors includes providing a gate insulatinglayer, depositing ZnO, SnO₂ or In₂O₃ onto at least a portion of asurface of the gate insulating layer, and annealing the ZnO, SnO₂ orIn₂O₃ for about 1 minute to about 2 hours at a temperature of about 300to about 1000° C. in an oxidative atmosphere.

The transistors may be included in optoelectronic display devices asswitches coupled to at least one display element. Another discloseddevice is a substantially transparent, dynamic random-access memorycell, comprising a substantially transparent capacitor coupled to thetransistor. A further application of the transistors is in substantiallytransparent inverters wherein the transistor is coupled to a loaddevice.

In general, the transistor structure includes a substrate, a gateelectrode, a gate insulator layer, a channel layer, a source and adrain. The channel layer may be positioned adjacent to the gateinsulator layer so that a surface of the channel layer is contiguouswith a surface of the gate insulator layer. The contact region of thechannel layer surface and the gate insulator layer surface is referredto herein as the channel layer/gate insulator layer interface. Inexemplary constructs, the channel layer insulating material is differentthan the gate insulator layer material and the channel layer/gateinsulator layer interface defines a discrete material boundary.

A feature of an embodiment of the transistor structure is that thechannel layer/gate insulator layer interface may define a conductingchannel for the flow of electrons from the source to the drain. In otherwords, the transistor may be classified as a “surface-channel” or“interface-channel” device. The applied gate voltage facilitateselectron accumulation in the channel layer/gate insulator layerinterface region. In addition, the applied voltage enhances electroninjection from the source to the channel layer/gate insulator layerinterface and electron extraction therefrom by the drain.

Another characteristic of the transistor structure is that selectedembodiments of the construct or combination of the channel layer and thegate insulator layer may exhibit an optical transmission of at leastabout 90%, more particularly at least about 95%, across the visibleportion (and/or infrared portion in certain variants) of theelectromagnetic spectrum. Each of the additional components of thestructure (i.e., substrate, gate electrode, source/drain terminals) maybe optionally opaque or substantially transparent depending upon thedesired end use of the transistor. In certain embodiments, thetransistor structure as a whole (and/or individual components of thetransistor) may exhibit an optical transmission of at least about 50%,more particularly at least about 70%, and most particularly at leastabout 90%, across the visible portion (and/or infrared portion incertain variants) of the electromagnetic spectrum.

A further feature of the FET disclosed herein is that it may easily befabricated as a thin film transistor (TFT). For example, relatively lowprocessing temperatures (e.g., not exceeding about 800° C.) may be usedand there is no need for ion implanting to set the channel thresholdvoltage and define the source and drain contacts in certain variants ofthe FET structure. Such TFTs typically are very useful in associationwith optoelectronic device as explained below in more detail.

The channel layer typically is made from a substantially insulatingmaterial that is also substantially transparent. A negligible amount ofelectrons is inherently available in the bulk portion of the channellayer since the channel layer is made from a substantially insulatingmaterial. In addition, the substantially insulating channel layer mayprovide inherent electrical isolation for multiple devices sharing acontinuous channel layer film (with patterned gate, source, and drainelectrodes defining each device). Such inherent device isolation meansthat patterning of the channel layer film is not necessary sinceconductivity at the channel layer/gate insulator layer is exhibited onlybeneath the patterned gate electrodes.

Illustrative materials for the channel layer include ZnO, SnO₂ andIn₂O₃. Insulating ZnO, SnO₂, and In₂O₃ may be made by an annealingprocess, particularly rapid thermal annealing (RTA). Such insulatingZnO, SnO₂ and In₂O₃ typically exhibit a bandgap of less than about 5 eV.

For example, a layer of ZnO may be deposited (e.g., by sputtering,chemical vapor deposition, spin coating, physical vapor deposition,vapor phase epitaxy, molecular beam epitaxy, etc.) and subsequentlyundergo annealing for about 1 minute to about 2 hours, more particularlyabout 1 minute to about 1 hour, and about 1 minute to about 5 minutes incertain instances, at a temperature of about 300 to about 1000° C.,particularly about 700 to about 800° C., in a substantially oxidativeatmosphere. Although not bound by any theory, it is believed that such aprocess should result in the incorporation of more oxygen into the ZnOlayer, thus reducing the oxygen vacancy concentration or degree ofoxygen deficiency. Oxygen vacancies or oxygen deficiency in ZnO canrender it n-type and conductive. High temperature (i.e., at least about700° C.) annealing in inert atmospheres such as argon may also produceinsulating ZnO. Although not bound by any theory, such highertemperature anneals may improve the ZnO crystallinity, thus improvingthe electron transport properties. Such insulating ZnO may or may not bedoped. If doped, the resistivity of the ZnO may also be enhanced bysubstitutional doping with an acceptor dopant such as, for example, N,Cu, Li, Na, K, Rb, P, As, and mixtures thereof.

Similarly, a layer of SnO₂ may be deposited (e.g., by sputtering,chemical vapor deposition, spin coating, physical vapor deposition,vapor phase epitaxy, molecular beam epitaxy, etc.) and subsequentlyundergo annealing for about 1 minute to about 2 hours, more particularlyabout 1 minute to about 1 hour, and about 1 minute to about 5 minutes incertain instances, at a temperature of about 300 to about 1000° C.,particularly about 700 to about 900° C., in a substantially oxidativeatmosphere. Although not bound by any theory, it is believed that such aprocess should result in the incorporation of more oxygen into the SnO₂layer, thus reducing the oxygen vacancy concentration or degree ofoxygen deficiency. Oxygen vacancies or oxygen deficiency in SnO₂ canrender it n-type and conductive. High temperature (i.e., greater thanabout 700° C.) annealing in inert atmospheres such as argon may alsoproduce insulating SnO₂. Although not bound by any theory, such highertemperature anneals may improve the SnO₂ crystallinity, thus improvingthe electron transport properties. The resistivity of the SnO₂ may alsobe enhanced by substitutional doping with an acceptor dopant such as,for example, Al, In, Ga, Bi, B, La, Sc, Y, Lu, Er, Ho, N, P, As, andmixtures thereof.

Also similarly, a layer of In₂O₃ may be deposited (e.g., by sputtering,chemical vapor deposition, spin coating, physical vapor deposition,vapor phase epitaxy, molecular beam epitaxy, etc.) and subsequentlyundergo annealing for about 1 minute to about 2 hours, more particularlyabout 1 minute to about 1 hour, and about 1 minute to about 5 minutes incertain instances, at a temperature of about 300 to about 1000° C.,particularly about 700 to about 900° C., in a substantially oxidativeatmosphere. Although not bound by any theory, it is believed that such aprocess should result in the incorporation of more oxygen into the In₂O₃layer, thus reducing the oxygen vacancy concentration or degree ofoxygen deficiency. Oxygen vacancies or oxygen deficiency in In₂O₃ canrender it n-type and conductive. High temperature (i.e., greater thanabout 700° C.) annealing in inert atmospheres such as argon may alsoproduce insulating In₂O₃. Although not bound by any theory, such highertemperature anneals may improve the In₂O₃ crystallinity, thus improvingthe electron transport properties. The resistivity of the In₂O₃ may alsobe enhanced by substitutional doping with an acceptor dopant such as,for example, Be, Mg, Ca, Sr, Ba, N, P, As, Zn, Cd, and mixtures thereof.

According to particular embodiments, the ZnO, SnO₂, or In₂O₃ layer maybe sputter deposited in an atmosphere that includes at least one sputtergas, and at least one film-modifying gas. The film-modifying gas may beany gas that can enhance the resistivity of the film via incorporationinto the film on an atomic or sub-atomic level. For example, afilm-modifying gas may be an oxidative gas whose molecules, atoms orions are incorporated into the film so that they occupy oxygen vacanciesor deficiencies in the film as described above. Another film-modifyinggas may be a dopant gas whose molecules, atoms or ions are incorporatedinto the film so that they increase the resistivity of the film.Illustrative sputter gases include Ar, Ne, and mixtures thereof.Illustrative oxidative gases include O₂, N₂O and mixtures thereof.Illustrative dopant gases include N₂, NH₃ and other gases containing thedopant species listed above. The concentrations of the gases in thesputter atmosphere may be varied depending upon the desiredcharacteristics of the film. For example, the concentration of oxidativegas may range from about 0 to about 50 volume percent. The concentrationof dopant gas may range from about 0 to about 50 volume percent. Theconcentration of sputter gas may range from about 0 to about 100 volumepercent. The sputtering conditions may also be varied depending upon thedesired characteristics of the film. For instance, the temperature mayrange from about room temperature to 600° C., and the pressure may rangefrom about 1 mTorr to about 50 mTorr. In a specific example, an undopedZnO target may be sputter deposited in an atmosphere that includes 80volume percent Ar, 10 volume percent N₂, and 10 volume percent O₂.

The thickness of the channel layer may vary, and according to particularexamples it can range from about 10 to about 500 nm. The channel lengthalso may vary, and according to particular examples it can range fromabout 1,000 to about 100,000 nm.

The gate insulator layer may be made from any material exhibitinginsulating properties required for gate insulators, particularly asubstantially transparent material. Gate insulator materials typicallyexhibit a bandgap of greater than about 5 eV. Illustrative materialsinclude substantially transparent materials such as aluminum-titaniumoxide (Al₂O₃/TiO₂), Al₂O₃, MgO, SiO₂, silicon nitride, and siliconoxynitride. One distinctive example of a substantially transparentmaterial is aluminum-titanium oxide grown by atomic layer deposition.The thickness of the gate insulator layer may vary, and according toparticular examples it can range from about 10 to about 300 nm. The gateinsulator layer may be introduced into the structure by techniques suchas chemical vapor deposition, sputtering, atomic layer deposition, orevaporation.

Source/drain terminals refer to the terminals of a FET, between whichconduction occurs under the influence of an electric field. Designersoften designate a particular source/drain terminal to be a “source” or a“drain” on the basis of the voltage to be applied to that terminal whenthe FET is operated in a circuit. The source and drain may be made fromany suitable conductive material such as an n-type material. The sourceand drain materials are optionally opaque materials or substantiallytransparent materials. Illustrative materials include transparent,n-type conductors such as indium-tin oxide (ITO), ZnO, SnO₂, or In₂O₃ oropaque metals such as Al, Cu, Au, Pt, W, Ni, or Ti. Especially usefulmaterials for the source and drain are those that can inject (andextract) electrons into the channel layer insulating material. Examplesof such electron injection materials include indium-tin oxide, LaB₆, andZnO:Al.

The source and drain may be introduced into the structure by techniquessuch as chemical vapor deposition, sputtering, evaporation, and/ordoping of the channel layer material via diffusion or ion implantation.The source and drain terminals may be fabricated such that they aregeometrically symmetrical or non-symmetrical.

The gate electrode may be made from any suitable conductive material.The gate electrode material is optionally an opaque material or asubstantially transparent material. Illustrative gate electrodematerials include transparent, n-type conductors such as indium-tinoxide (ITO), ZnO, SnO₂, or In₂O₃, or opaque metals such as Al, Cu, Au,Pt, W, Ni, or Ti. The thickness of the gate electrode may vary, andaccording to particular examples it can range from about 50 to about1000 nm. The gate electrode may be introduced into the structure bychemical vapor deposition, sputtering, evaporation and/or doping.

“Substrate”, as used herein, refers to the physical object that is thebasic workpiece that is transformed by various process operations intothe desired microelectronic configuration. A substrate may also bereferred to as a wafer. Wafers may be made of semiconducting,non-semiconducting, or combinations of semiconducting andnon-semiconducting materials. The substrate may be made from anysuitable material. The substrate material is optionally an opaquematerial or a substantially transparent material. Illustrative substratematerials include glass and silicon. The thickness of the substrate mayvary, and according to particular examples it can range from about 100μm to about 1 cm.

Electrical contact to the gate electrode, source, drain and substratemay be provided in any manner. For example, metal lines, traces, wires,interconnects, conductors, signal paths and signaling mediums may beused for providing the desired electrical connections. The related termslisted above, are generally interchangeable, and appear in order fromspecific to general. Metal lines, generally aluminum (Al), copper (Cu)or an alloy of Al and Cu, are conductors that provide signal paths forcoupling or interconnecting, electrical circuitry. Conductors other thanmetal may also be utilized.

An illustrative n-channel operation of the transistor involves applyinga positive voltage to the gate electrode, grounding the source, andapplying a positive voltage to the drain. For example, a voltage ofabout 5 to about 40 V may be applied to the gate electrode and the drainduring operation. The threshold voltage may range from about 1 to about20 V. Electrons flow from the source, along the conducting channelcreated at the channel layer/gate insulator layer interface, and out ofthe transistor through the drain. The effective mobility of theelectrons at the interface may vary depending upon the specificstructure, but could range, for example, from about 0.05 to about 20cm²V⁻¹s⁻¹. Simply removing the positive voltage applied to the gateelectrode turns the transistor off since the transistor is anenhancement-mode transistor.

The transistor structures disclosed herein may be used for fabricatingchips, integrated circuits, monolithic devices, semiconductor devices,and microelectronic devices. One example of a microelectronic device isan optoelectronic device. An illustrative optoelectronic device is anactive-matrix liquid-crystal display (AMLCD).

One exemplar device is an optoelectronic display device that includeselements having electrodes and an electro-optical material disposedbetween the electrodes. A connection electrode of the transparenttransistor may be connected to an electrode of the display element,while the switching element and the display element overlap one anotherat least partly. An optoelectronic display element is here understood tobe a display element whose optical properties change under the influenceof an electrical quantity such as current or voltage such as, forexample, an element usually referred to as liquid crystal display (LCD).The presently detailed transparent transistor is sufficiently fast forswitching the display element at such a high frequency that the use ofthe transparent transistor as a switching element in a liquid crystaldisplay is possible. The display element acts in electrical terms as acapacitor that is charged or discharged by the accompanying transparenttransistor. The optoelectronic display device may include many displayelements each with its own transparent transistor, for example, arrangedin a matrix. The transparent transistors may be arrayed for LCD devicesas described, for example, in Kim, “Thin-Film-Transistor Device Design”,Information Display 2/02, p. 26 (2002).

One specific example of an AMLCD cell circuit is depicted in FIG. 11.The AMLCD cell circuit includes a transistor 60 as presently described,and a LCD pixel 61 electrically coupled thereto. The transistor 60 andthe LCD pixel 61 together form a transistor/pixel cell 62. In thearrangement shown, the transistor 60 is electrically coupled to the LCDpixel 61 via the drain electrode. The gate electrode of the transistor60 is electrically coupled to a row or control line 63 that receiveson/off input for the transistor 60. The source electrode of thetransistor 60 is electrically coupled to a column or data line 64 thatreceives a signal for controlling the LCD pixel 61.

Other examples of microelectronic devices that could employ thetransistor structure shown herein include inverters, analog amplifiersand single-transistor dynamic random-access memory (DRAM) cells, andlike devices.

For instance, a transparent enhancement-mode transistor whose source isconnected to one terminal of a transparent capacitor, while the otherterminal of the capacitor is grounded, constitutes a transparentsingle-transistor dynamic random-access memory (DRAM) cell. In such aDRAM cell, information is stored as charge on a capacitor, with theenhancement-mode transistor serving as an access transistor thatcontrols the capacitor charge state. Usually in such a DRAM cell, alogic 0 is represented by negligible capacitor charge and aconcomitantly small capacitor voltage. In contrast, a logic 1 isobtained by charging the capacitor, thus increasing the capacitorvoltage until it approaches the power supply voltage.

The entire DRAM cell described herein, or a portion thereof, istransparent. Fabricating transparent capacitors and connecting them to atransparent transistor to realize a DRAM cell can be accomplished usingvarious techniques. Specifically, a transparent capacitor may beconstructed by sandwiching a transparent insulator layer, usingmaterials such as Al₂O₃ or SiO₂, between two transparent conductors,using materials such as indium-tin oxide, ZnO, or SnO₂.

One specific example of a DRAM cell circuit is depicted in FIG. 12. TheDRAM cell circuit includes a transistor 70 as presently described, and astorage capacitor 71 electrically coupled thereto. The transistor 70 andthe storage capacitor 71 together form a transistor/capacitor cell 72.In the arrangement shown, the transistor 70 is electrically coupled tothe storage capacitor 71 via the drain electrode. The gate electrode ofthe transistor 70 is electrically coupled to a row or write line 73 thatreceives on/off input for the transistor 70. The source electrode of thetransistor 70 is electrically coupled to a column or data line 74 thatreceives a signal for controlling what is stored on the storagecapacitor 71.

Illustrative examples of specific transistor structures are shown inFIGS. 1-3 and FIGS. 8-10. The specific examples described below are forillustrative purposes and should not be considered as limiting the scopeof the appended claims. In FIGS. 1-3 and 8-10 like reference numeralsrefer to like elements unless otherwise indicated.

FIG. 1

A TFT structure 1 is illustrated that was fabricated on a one-inch byone-inch thick composite substrate. The platform includes a glasssubstrate 2, a 200 nm thick, indium-tin oxide (ITO) gate electrode 3coated on the substrate 2, and a 200 nm thick, aluminum-titanium oxidegate insulator layer 4.

A ZnO channel and an ITO source/drain electrode film was deposited viaion beam sputtering in 10⁻⁴ Torr of Ar/O₂ (80%/20%); the substrate wasunheated during deposition. The ZnO channel layer 5 (100 nm thick), anITO source electrode 6 (300 nm thick) and, an ITO drain electrode 7 (300nm thick) were defined using a shadow mask. The resulting structuredefines a channel layer/gate insulator layer interface 8. A 300° C.rapid thermal anneal (RTA) in Ar immediately prior to both the ZnO andITO depositions served to remove adsorbed contaminants from the exposedsurface, yielding a noticeable improvement in film quality (particularlyfor ITO films). After deposition of the ZnO layer, a RTA (typically inO₂ or Ar, at 600 to 800° C.) was employed to increase the ZnO channelresistivity and to improve the electrical quality of the channellayer/gate insulating layer interface 8. Following deposition of the ITOsource/drain electrodes, a 300° C. RTA in O₂ was used to improve thetransparency of the ITO layer. In the transistor structure 1 thesource/drain electrodes 6 and 7 are disposed on the top surface of thechannel layer 5 (from a vertical perspective) and the gate electrode 3and channel layer 5 are disposed, respectively, on opposing surfaces ofthe gate insulator layer 4. Consequently, structure 1 allows for hightemperature processing of the ZnO channel layer 5 prior to depositionand processing of the ITO source/drain electrodes 6 and 7. Certainelectrical and physical characteristics of the TFT structure 1 wereevaluated as described below and illustrated in FIGS. 4-7.

With reference to FIG. 4, n-channel, enhancement-mode behavior isobtained as demonstrated by the fact that a positive gate voltage inexcess of ˜15 V (the threshold) is required to obtain appreciabledrain-source current. These I_(DS)-V_(DS) curves exhibit prototypicalFET characteristics; of particular significance is the flatness of thesecurves at large drain voltages (i.e. they exhibit ‘hard’ saturation).The drain and gate voltages employed are rather large compared toconventional FETs; gate and drain voltages can be reduced to the rangeexpected for typical FET operation (i.e. ˜5-10 V), by simply reducingthe gate insulator thickness. In the TFT structure 1 the insulatorthickness is ˜200 nm, as optimized for electroluminescent displayapplications; if an otherwise identical insulator is rescaled to athickness of 20 nm, the gate and drain voltages will be reduced by afactor of approximately 10.

The I_(DS) of structure 1 is currently rather small (i.e., I_(DS) (max)is about 6 μA in FIG. 4). A larger I_(DS) may be desirable for mostapplications. The magnitude of I_(DS) is determined by two factors. Oneis the effective mobility of the channel electrons, μ_(eff) (about0.05-0.2 cm²V⁻¹s⁻¹ for the TFT structure 1). Process/device optimizationshould result in an improvement in μ_(eff) by a factor of about 2 to 100which will lead to a corresponding increase in I_(DS). The second factoris the aspect ratio. The aspect ratio of the TFT structure 1 (thephysical width of the gate, Z, divided by the length of the gate, L) isabout 2 (with Z=2 L=6000 μm). A larger aspect ratio will lead to alarger I_(DS).

FIG. 5 illustrates the I_(DS)-V_(GS) characteristics of the TFTstructure 1 at three different drain voltages. This figure shows thatthere is a factor of 10⁵-10⁶ difference between the ‘on’ and ‘off’currents when the transistor is used as a switch.

FIG. 6 shows the transfer characteristics of the TFT structure 1 when itis employed as an inverter. A ZnO transparent thin-film resistor (R=70MΩ) is used as the inverter passive load with a power supply voltageV_(DD)=40 V. A logic swing of about 15 V between 15 and 30 V is clearlyevident from this curve. This constitutes a demonstration of the use ofthe presently described transparent TFT as a transparent inverter. Inits simplest implementation, a logic inverter is comprised of twoconstituents: a transistor coupled to a load device. The load device maybe a resistor, as employed in this example. Alternatively, a depletion-or enhancement-mode transistor may also be used as load devices,typically offering superior performance. The fundamental property of alogic inverter is that it performs a logical not operation, in which alogic 0 (1) input produces a logic 1 (0) output. Successful achievementof a transparent logic inverter, as described herein, is significantsince the inverter is the most basic building block for achievingtransparent digital electronics. Optimization of the transparent thinfilm transistor via reducing the insulator thickness, reducing physicaldimensions, and increasing the current drive capability (increasedaspect ratio and effective mobility) will lead to a significantreduction in the required power supply voltage for inverter operation.

One specific example of a logic inverter circuit is depicted in FIG. 13.The logic inverter circuit includes a transistor 80 as presentlydescribed. The gate electrode of the transistor 80 is electricallycoupled to a voltage input (V_(in)), the source electrode of thetransistor 80 is electrically coupled to ground, and the drain electrodeof the transistor 80 is electrically coupled to a load 81 and a powersource (V_(DD)). The load 81 may be a transparent thin-film resistor ora transparent thin-film transistor. The voltage (V_(out)) out of thecircuit is controlled by whether V_(in) turns the transistor 80 on oroff.

Transparent transistors may also be employed in amplifier applications.For example, the inverter structures described above can also functionas simple analog inverting amplifiers. With the appropriate DC bias atthe input, a small input signal (superimposed upon the DC bias) isamplified by the inverter transfer characteristic. In addition to suchsimple amplifier configurations, these transistors could be directlyapplied in arbitrary amplifier configurations, with the limitation thatthe maximum operating frequency will be relatively low due to the lowmobility of these devices.

One specific example of an inverting amplifier circuit is depicted inFIG. 14. The inverting amplifier circuit includes a transistor 90 aspresently described. The gate electrode of the transistor 90 iselectrically coupled to a voltage input signal (V_(in)) and a DC bias(V_(bias)). The source electrode of the transistor 90 is electricallycoupled to ground, and the drain electrode of the transistor 90 iselectrically coupled to a load 91 and a power source (V_(DD)). The load91 may be a transparent thin-film resistor or a transparent thin-filmtransistor.

FIG. 7 shows the optical transmission of the TFT structure 1 through thesource 6 or drain 7 (optical transmission through the channel, not shownhere, is higher than through the source or drain). The averagetransmission in the visible portion of the electromagnetic spectrum(450-700 nm) is about 90% (about 95% through the channel). Visually, thetransparent TFT structure is essentially invisible; a slight tinting ofthe glass substrate is apparent upon close inspection.

FIG. 2

In another transparent TFT structure 10 version shown in FIG. 2, asource electrode 11 (100 nm thick) and a drain electrode 12 (100 nmthick) were made by selectively doping the ends of a ZnO channel layer13 (100 nm thick) with In (or any other suitable n-type dopant). Thiswas accomplished by ion beam sputter depositing a thin (about 5 nm) ITOlayer using the source/drain shadow mask before depositing the ZnOchannel film. A subsequent high-temperature (˜600-800° C.) annealingstep was performed to diffusion-dope the ZnO, thus forming n-type dopedsource/drain regions 11 and 12. The diffusion-doping RTA may alsofunction as the oxidizing RTA for the ZnO. ITO contacts may be placedover the source and drain regions to provide better electrical contact.The substrate 2, gate electrode 3, gate insulator layer 4, and channellayer/gate insulator layer interface 8 are the same as in FIG. 1.

FIG. 3

In a third variation of a TFT structure 20, an ITO source electrode 21(300 nm thick) and ITO drain electrode 22 (300 nm thick) are depositedprior to formation of a ZnO channel layer 23 (100 nm thick). The ZnOchannel layer 23 is subsequently deposited conformally over the ITOsource/drain electrodes 21 and 22. After deposition of the ZnO, a 700°C. Ar anneal was performed, followed by a 300° C. oxygen anneal. Thesubstrate 2, gate electrode 3, gate insulator layer 4, and channellayer/gate insulator layer interface 8 are the same as in FIG. 1.

FIG. 8

A fourth variation of a TFT structure 30 is shown in FIG. 8. The TFTstructure 30 includes a glass substrate 2 upon which is disposed asource electrode 35 and a drain electrode 36. A channel structure 37 isprovided that includes a bulk section 38 positioned between the sourceelectrode 35 and the drain electrode 36 and adjacent to the glasssubstrate 2. The channel structure 37 also includes an interface section39 that is integral with the bulk section 38, and interposed between agate insulator layer 34 and the source electrode 35 and the drainelectrode 36, respectively. The interface section 39 may overlap all oronly a portion of each of the source electrode 35 and the drainelectrode 36. The interface section 39 and the gate insulator layer 34form a channel layer/gate interface layer 31 that defines a conductingchannel for the flow of electrons from the source to the drain. A gateelectrode 33 is disposed on the top surface (from a verticalperspective) of the gate insulator layer 34. In other words, the gateelectrode 33 and the channel structure 37 are provided on opposingsurfaces of the gate insulator layer 34.

The TFT structure 30 may be fabricated, for example, by depositing andpatterning a film that defines the source electrode 35 and the drainelectrode 36. For instance, a 500 Å ITO source/drain electrode film maybe sputtered onto the glass substrate 2. The source and drain patterningmay be accomplished via shadow masking or photolithography. Thesource/drain electrode film could optionally be annealed. The channelstructure 37 may then be deposited and patterned over the sourceelectrode 35, the drain electrode 36, and the substrate 2. For example,a 500 Å ZnO film may be sputter deposited, and then patterned via shadowmasking or photolithography. The ZnO film could optionally be annealed.Subsequently, the gate insulator layer 34 may then be deposited andpatterned over the channel structure 37. For example, a 2000 Å Al₂O₃film may be sputter deposited, and then patterned via shadow masking orphotolithography. Vias may be formed through the gate insulator layer 34to electrically connect to the source electrode 35 and the drainelectrode 36. The Al₂O₃ film could optionally be annealed. The gateelectrode 33 may then be deposited and patterned over the gate insulatorlayer 34. For example, a 2000 Å ITO film may be sputter deposited, andthen patterned via shadow masking or photolithography. The ITO filmcould optionally be annealed.

FIG. 9

A fifth variation of a TFT structure 40 is shown in FIG. 9. The TFTstructure 40 includes a glass substrate 2 upon which is disposed achannel layer 41. A source electrode 43 and a drain electrode 42 areprovided on a surface of the channel layer 41 opposing the surface thatis adjacent to the glass substrate 2. A gate insulator layer 44 isdisposed over the channel layer 41, the source electrode 43, and thedrain electrode 42. A gate electrode 45 is disposed on the top surface(from a vertical perspective) of the gate insulator layer 44. In otherwords, the gate electrode 45 and the channel layer 41 are provided onopposing surfaces of the gate insulator layer 44. The resultingstructure defines a channel layer/gate insulator layer interface 46.

The TFT structure 40 may be fabricated, for example, by depositing andpatterning a film that defines the channel layer 41. For instance, a 500Å ZnO film may be sputter deposited, and then patterned via shadowmasking or photolithography. The ZnO film could optionally be annealed.The source electrode 43 and the drain electrode 42 may then be depositedand patterned. For example, a 500 Å ITO source/drain electrode film maybe sputtered deposited, and then patterned via shadow masking orphotolithography. The source/drain electrode film could optionally beannealed. Subsequently, the gate insulator layer 44 may then bedeposited and patterned over the channel layer 41, the source electrode43, and the drain electrode 42. For example, a 2000 Å Al₂O₃ film may besputter deposited, and then patterned via shadow masking orphotolithography. Vias may be formed through the gate insulator layer 44to electrically connect to the source electrode 43 and the drainelectrode 42. The Al₂O₃ film could optionally be annealed. The gateelectrode 45 may then be deposited and patterned over the gate insulatorlayer 44. For example, a 2000 Å ITO film may be sputter deposited, andthen patterned via shadow masking or photolithography. The ITO filmcould optionally be annealed.

FIG. 10

A sixth variation of a TFT structure 50 is shown in FIG. 10. The TFTstructure 50 includes a glass substrate 2 upon which is disposed achannel layer 51, a source electrode 52, and a drain electrode 53. Agate insulator layer 54 is disposed over the channel layer 51, thesource electrode 52, and the drain electrode 53. A gate electrode 55 isdisposed on the top surface (from a vertical perspective) of the gateinsulator layer 54. In other words, the gate electrode 55 and thechannel layer 51 are provided on opposing surfaces of the gate insulatorlayer 54. The resulting structure defines a channel layer/gate insulatorlayer interface 56.

The TFT structure 50 may be fabricated, for example, by depositing andpatterning a film that defines the channel layer 51. For instance, a 500Å ZnO film may be sputter deposited, and then patterned via shadowmasking or photolithography. The ZnO film could optionally be annealed.The source electrode 52 and the drain electrode 53 may be made byselectively doping the ends of the channel layer 51 with In, Al, Ga, orany other suitable n-type dopant. Subsequently, the gate insulator layer54 may then be deposited and patterned over the channel layer 51, thesource electrode 52, and the drain electrode 53. For example, a 2000 ÅAl₂O₃ film may be sputter deposited, and then patterned via shadowmasking or photolithography. Vias may be formed through the gateinsulator layer 54 to electrically connect to the source electrode 52and the drain electrode 53. The Al₂O₃ film could optionally be annealed.The gate electrode 55 may then be deposited and patterned over the gateinsulator layer 54. For example, a 2000 Å ITO film may be sputterdeposited, and then patterned via shadow masking or photolithography.The ITO film could optionally be annealed.

Having illustrated and described the principles of the disclosed devicesand methods with reference to several embodiments, it should be apparentthat these devices and methods may be modified in arrangement and detailwithout departing from such principles.

1. A method for making an enhancement mode, field effect transistorcomprising: depositing ZnO, SnO₂, or In₂O₃ onto at least a portion of asurface of a gate insulating layer; and annealing the ZnO, SnO₂, orIn₂O₃ for about 1 minute to about 2 hours at a temperature of about 300to about 1000° C. in an oxidative or inert atmosphere.
 2. The methodaccording to claim 1, wherein ZnO is deposited.
 3. The method accordingto claim 1, wherein the gate insulator layer comprises a substantiallytransparent material.
 4. The method according to claim 1, wherein theannealing temperature is about 700 to about 800° C.
 5. The methodaccording to claim 1, further comprising depositing on the ZnO, SnO₂ orIn₂O₃ layer at least one material for forming a source and a drain. 6.The method according to claim 1, further comprising depositing on thegate insulating layer at least one material for forming a source and adrain prior to depositing the ZnO, SnO₂, or In₂O₃.
 7. The methodaccording to claim 6, wherein the material for forming a source and adrain is ion beam sputtered deposited onto the gate insulating layer,and the annealing of the ZnO diffusion dopes the ZnO with the source anddrain material.
 8. A method for making an enhancement mode, field effecttransistor comprising: depositing ZnO, SnO₂ or In₂O₃ onto at least aportion of a surface of a gate insulating layer; and treating the ZnO,SnO₂ or In₂O₃ such that the treated ZnO, SnO₂, or In₂O₃ has a higherresistivity and a lower oxygen vacancy concentration relative to theuntreated ZnO, SnO₂, or In₂O₃.
 9. The method according to claim 2,further comprising introducing an acceptor dopant into the ZnO.
 10. Themethod according to claim 1, wherein the depositing of ZnO, SnO₂, orIn₂O₃ comprises sputter depositing the ZnO, SnO₂, or In₂O₃ in anatmosphere that includes at least one sputter gas and at least one gasthat can modify a film formed by the ZnO, SnO₂, or In₂O₃.
 11. The methodaccording to claim 10, wherein the film-modifying gas comprises at leastone gas selected from an oxidative gas or a dopant gas.
 12. The methodaccording to claim 11, wherein the oxidative gas comprises oxygen andthe dopant gas comprises nitrogen.
 13. The method according to claim 1,wherein the ZnO, SnO₂, or In₂O₃ is annealed for about 1 minute to about5 minutes.
 14. The method according to claim 1, wherein the depositedand annealed ZnO, SnO₂, or In₂O₃ forms a channel layer comprising asubstantially insulating, substantially transparent, material.
 15. Themethod according to claim 2, wherein the ZnO is vapor deposited.
 16. Themethod according to claim 1, wherein the field effect transistorexhibits an optical transmission through the field effect transistor ofat least about 70% in the visible portion of the electromagneticspectrum.
 17. The method according to claim 1, wherein the In₂O₃ or SnO₂is deposited via chemical vapor deposition, sputtering, spin-coating,physical vapor deposition, vapor phase epitaxy, or molecular beamepitaxy.
 18. The method according to claim 1, wherein In₂O₃ isdeposited.
 19. The method according to claim 10, wherein the annealingtemperature is at least about 700° C.
 20. The method according to claim1, wherein the annealing temperature is at least about 700° C.
 21. Themethod according to claim 11, wherein the oxidative gas comprises O₂,N₂O or a mixture thereof.
 22. The method according to claim 11, whereinthe dopant gas comprises N₂, or NH₃.